Redundancy Analysis using Genetic Algorithm
Published in INDICON 2021, 2022
Abstract – During the manufacturing of a DRAM chip, external impurities, faulty deposition steps, or manufacturing errors could generate chips with faulty memory cells rendering the chip unusable. To overcome these faulty memory cells, redundancies are included in the memory, allowing mapping of faulty rows and columns to these redundancies. The process of mapping faulty lines to redundancies is called Redundancy Analysis. Redundancy Analysis is an NP-complete problem. In this paper, we propose a memory repair solution based on the Genetic Algorithm to repair the memory efficiently without compromising on the yield compared to that of the existing heuristic algorithms. Performance comparison to the best heuristic and an exhaustive search algorithm gave a promising result with an average repair rate improvement of 6.48% and theoretical run time improvement of 33 times respectively. Genetic Algorithm can be used directly in the production line to improve the wafer yield. A compound algorithm was also developed in which the population initialization was done with the solution of a heuristic algorithm with a yield improvement of 0.5% over the genetic algorithm with random initialization.
Recommended citation: H. K. Thacker, A. Kumar, A. Gupta, K. K. Jagannathachar and D. Yoon, “Redundancy Analysis using Genetic Algorithm,” 2021 IEEE 18th India Council International Conference (INDICON), 2021, pp. 1-6, doi: 10.1109/INDICON52576.2021.9691562.