A Deep Learning Model for Redundancy Analysis Algorithm Recommendation

Abstract – Manufacturing errors, external impurities or faulty deposition during chip fabrication could generate chips with faulty memory cells, rendering the chip unusable. To repair these faulty memory cells, redundancies are included in the memory in the form of spare rows and columns. The process of mapping faulty lines to redundant cells is Redundancy Analysis. Applying a uniform Redundancy Analysis algorithm on the wafers or running algorithms sequentially one after the other would either compromise on the repair time or wafer yield. An end-to-end solution for memory repair is proposed in this paper. A clustering algorithm to classify, identify and extract features from chip errors on a wafer is proposed. These features along with other derived parameters are used as an input to the neural network recommender system to select algorithms allowing an increase in the wafer yield keeping a low repair time per wafer. We have performed comparisons of the generated result with and without clustering and with other methods of classification of chips for Redundancy Analysis algorithm selection such as Decision Trees. Experimental results demonstrate that this solution out-performs the heuristic algorithmic solutions by 9.1% and 32.9% in terms of yield for medium and high error rates.

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Recommended citation: A. Kumar, H. K. Thacker, A. Gupta, K. K. Jagannathachar and D. Yoon, “A Deep Learning Model for Redundancy Analysis Algorithm Recommendation,” 2021 IEEE 18th India Council International Conference (INDICON), 2021, pp. 1-6, doi: 10.1109/INDICON52576.2021.9691578.